Provides IP cores, supporting development tools for embedded processors based on SPARC architecture. Key product: LEON synthesizable processor model, full development environment, and library of IP cores, GRLIB. Göteborg, Sweden.

Functional SPARC compatible processor core. Fault tolerant version of LEON2, derived from LEON-1 integer unit, implemented as highly configurable, synthesizable VHDL model. Runs on Altera, Mietec, Temic MG2, Xilinx. Designed for outer space uses. Open source, GPL. European Space Agency, ESA.

Sun Microsystems initiative to create open source community and participation in processor architecture development; news, documents, analysis, downloads.

Designs and supports open-source RISC processors, systems, peripherals; sells S1 Core, a 64-bit Wishbone-compliant CPU Core based on reduced Sun Microsystems OpenSPARC T1 microprocessor. Catania, Italy; Bristol, UK.

Announcement of open source LEON SPARC architecture; Google Groups.

Brief story and analysis; by Craig Matsumoto; TechWeb.

Download full MicroSPARC-IIep design for free under terms of Sun Community Source License. [CNET News.com]

Sun Microsystems announces: for research uses, it extends its new Community Source Licensing model to picoJava and SPARC architectures; the first time a company made major microprocessor intellectual property available via open licensing.

Open source version of UltraSPARC T1 processor, with CoolThreads technology; high throughput, low power, for high performance per watt; 32 simultaneous processing threads, uses about as much power as a light bulb. SunSource.net.

This core (codename Sirocco) is one 64-bit core from the OpenSPARC T1 8 core processor (codename Niagara), plus a Wishbone bridge, reset controller, and basic interrupt controller, to make it easy for engineers to integrate the design. SunSource.net.

Processor implementation for field programmable gate arrays. SunSource.net.

Main Sun pages on project: links, articles, documents, FAQ, contest.